1. Field of the Invention
The present invention relates to an image defect inspection apparatus for detecting a defect on the surface of a sample based on a captured image of the surface of the sample, and more particularly to an image defect inspection apparatus which acquires a plurality of patterns by scanning a sample under inspection, such as a semiconductor wafer, a photomask substrate, a liquid crystal display panel substrate, or a liquid crystal device substrate, on which a plurality of patterns that should be identical to each other are formed in an orderly repeating fashion, and compares the corresponding portions of the patterns.
2. Description of the Related Art
A number of identical chips (dies) are formed in an orderly repeating fashion on a semiconductor wafer. In the semiconductor device fabrication process, inspection is performed in the middle or at the end of the process to check the formed dies for defects, and if any defect is detected, the defect information is immediately fed back to the fabrication process thereby improving the fabrication yield. For this purpose, image defect inspection is performed by capturing optical patterns of the dies and detecting the presence or absence of defects in the patterns.
To obtain a high-resolution image, the image of a semiconductor wafer is projected onto a one-dimensional image sensor, and the semiconductor wafer scanned by the one-dimensional image sensor by moving one relative to the other, thus forming the image of the semiconductor wafer. FIG. 1 is a diagram showing an example of a scan path for acquiring an image of a semiconductor wafer 100 on which a plurality of dies 101 are formed in an orderly repeating fashion.
As shown in FIG. 1, a number of semiconductor chips (dies) 110 are formed in an orderly repeating fashion on the semiconductor wafer 100, and the image of the entire surface of the semiconductor wafer 100 is acquired by scanning the surface along the scan path 102. In the scan path shown here, first the lower portions of the dies in a given row are scanned from left to right, and then the upper portions of the dies in the same row are scanned from right to left, but as a variant, after the lower portions of the dies in a given row are scanned from left to right, the lower portions of the dies in the next row may be scanned from right to left.
FIG. 2 is a diagram explaining the scanning operation in further detail. In the example shown, the image of the dies 101 in each row is acquired by four scans 102-1 to 102-4. The image obtained by one scan is a long and narrow strip-like image called a “swath image” which has a width W corresponding to the length of the light-sensitive area of the one-dimensional image sensor used for the image formation. In the illustrated example, a swath image SW1 is obtained by the scan 102-1, and a swath image SW2 by the scan 102-2.
When the sample under inspection is an array of memory dies, each die 101 has a peripheral circuit portion 111 and a cell portion 112, as shown in the figure. The peripheral circuit portion 111 contains randomly arranged patterns, while the cell portion 112 is made up of identical cell patterns repeated at a prescribed pitch.
FIGS. 3A and 3B are diagrams explaining a method of defect inspection when identical patterns are arranged in an orderly repeating fashion as described above. A method for making a comparison of corresponding patterns between two dies is called a single detection. In a single detection, if the patterns of the two dies do not match, there is a defect in either one of the dies, however there is no way of telling which die contains the defect.
Accordingly, as shown in FIG. 3A, each die is sequentially compared with the dies adjacent on both sides, one on each side, that is, a total of two comparisons are made for the same portion. This method is called a double detection. In a double detection, if the same portion of the die under inspection does not match the corresponding portions of the two adjacent dies, then it can be determined that the die under inspection contains the defect.
For example, when a comparison was made between the dies 101-1 and 101-2, as shown in FIG. 3A, a mismatch was detected for a certain portion because the difference between the two image data for that portion was larger than a threshold value, and when the die 101-2 was further compared with the die 101-3, a mismatch was detected for the same portion; in this case, it is determined that that portion of the die 101-2 contains the defect. In a like manner, comparisons are sequentially made between adjacent dies, such as between the dies 101-3 and 101-4, and so on.
As shown in FIG. 2, the peripheral circuit portion 111 is a portion containing randomly arranged patterns, but the cell portion 112 is made up of identical cell patterns repeated at a prescribed pitch. In view of this, for the inspection of the peripheral circuit portion 111, a comparison is made between adjacent dies as described above, i.e., a die-to-die comparison, but for the inspection of the cell portion 112, the image is split at the cell pattern repeat pitch P, and the inspection is performed by sequentially comparing adjacent cell patterns in accordance with the double detection. This method is called a cell-to-cell comparison.
FIG. 3B is a diagram explaining the cell-to-cell comparison method; as shown, the cell patterns are repeated at pitch P, and comparisons are sequentially made between adjacent cell patterns, such as between the cell patterns 121-1 and 121-2, then between the cell patterns 121-2 and 121-3, and so on. Compared with the die-to-die comparison, the cell-to-cell comparison, in which a comparison is made between patterns located relatively close to each other, is less susceptible to noise caused by unevenness of wafer color, image registration error, etc., and hence has the advantage of being able to achieve high detection sensitivity. It is therefore desirable that the inspection of the cell portion containing the repeated cell patterns be performed based on the cell-to-cell comparison, and that the inspection of the peripheral circuit portion be performed based on the die-to-die comparison.
FIG. 4 is a diagram showing an internal configuration for performing the die-to-die comparison inspection in a prior art image defect inspection apparatus (surface inspection machine) for semiconductor wafer inspection. As will be described later, such a configuration is generally implemented as an image processing unit using a computer. The configuration and operation for performing the die-to-die comparison inspection will be briefly described below.
The image defect inspection apparatus 1 comprises: a stage 11 movable at least in the XY plane by holding a semiconductor wafer 100 thereon; an image capturing unit 12, disposed above the stage 11, for outputting an image signal by capturing an image of the surface of the wafer 100; an analog-digital converter 13 for converting the analog image signal, output from the image capturing unit 12, into digital image data; an image processing unit 20 for detecting a defect existing on the surface of the wafer 100 by performing prescribed image processing based on the image data; and an image transferring unit 14 for receiving the image data from the analog-digital converter 13 and transferring it into the image processing unit 20.
When the image capturing unit 12 is scanned in the main scanning directions 102-1 to 102-4 as shown in FIG. 2 by moving the stage 11 thereby moving the image capturing unit 12 relative to the wafer 100, a strip-like swath image will be obtained for each main scan.
When the swath image is input via the analog-digital converter 13 and the image transferring unit 14, the image defect inspection apparatus 1 divides the swath image into small regions of a prescribed size, called the “frames.” The defect detection such as the die-to-die comparison and/or cell-to-cell comparison described above is performed on a frame-by-frame basis. FIG. 5 is a diagram showing an example of how the swath image is divided into the plurality of frames.
First, the swath SW is divided into n regions in the direction orthogonal to the main scanning direction, i.e., in the longitudinal direction of the image capturing unit 12 constructed from a one-dimensional line sensor. For example, when reading out the one-dimensional image data from the image capturing unit 12, the image is divided into n regions at intervals of a predetermined number of pixels, thereby dividing the swath SW into a plurality of image data channels consisting of channel 1 to channel n.
The image data divided into the channels is further divided at intervals of a predetermined number of pixels (in the illustrated example, i pixels) in the main scanning direction. More specifically, when the pixel coordinate along the main scanning direction is designated as “line,” each channel of image data in the illustrated example is divided into image blocks comprising image data from line 1 to line i, image data from line (i+1) to line (2×i), and so on.
That is, each small region, i.e., a frame that serves as the unit on which the defect detection such as the die-to-die comparison and/or cell-to-cell comparison is performed, is obtained by dividing each swath SW into N channels in the longitudinal direction of the image capturing unit 12 and further dividing each channel at intervals of i lines in the main scanning direction.
Turning back to FIG. 4, the image processing unit 20 comprises n multiprocessing units MP1 to MPn (MP4 to MPn not shown) which inspect the n image data channels respectively, and an image processing management unit (IPM) 21 which receives defect information from the multiprocessing units MP1 to MPn as information concerning the defects that the respective multiprocessing units MP1 to MPn detected from the respective image data channels by performing the inspection in parallel, and which consolidates the thus received defect information.
In the following description, when collectively referring to the n multiprocessing units MP1 to MPn, the designation “MPx” referring to the xth multiprocessing unit may be used to generally represent them.
The n multiprocessing units MP1 to MPn are identical in configuration. Each multiprocessing unit comprises m processing units. In the illustrated example, the multiprocessing unit MP1 comprises processing units PU11 to PU1m (PU14 to PUm not shown).
In the following description, the m processing units provided in the xth multiprocessing unit MPx are designated as “PUx1” to “PUxm”, respectively; when collectively referring to the m processing units PUx1 to PUxm, the designation “PUxy” referring to the yth processing unit may be used to generally represent them.
In each multiprocessing unit MPx, each channel of input image data is divided into frames, and the defect detection is performed on a frame-by-frame basis. Each multiprocessing unit MPx comprises m processing units PUx1 to PUxm that can operate in parallel. With these m processing units PUx1 to PUxm operating in parallel to detect defects in the respectively different frames, the multiprocessing unit MPx simultaneously processes m frames in parallel.
Each of the processing units PUx1 to PUxm, upon detecting a defect, creates defect information for each detected defect and outputs the defect information.
The defect information output in parallel from the respective processing units PUx1 to PUxm is consolidated into a set of defect information by a processor unit PUx provided in each multiprocessing unit MPx, and sent to the IPM 21.
The suffix “x” in the processor unit PUx indicates that the processor unit PUx is provided in the xth multiprocessing unit MPx; for example, in FIG. 4, the processor unit PU1 provided in the first multiprocessing unit MP1 is shown. The processor unit PUx may be implemented using, for example, a single board computer (SBC) which is a computing means implemented on a single board.
The processing units PU11 to PUnm are also identical in configuration. Taking the processing unit PU11 shown in FIG. 4 as a representative example, the processing unit PU11 comprises a processor element PE11, a memory M11, and a line counter LC11 to be described later.
In the memory M11, there are allocated an area for storing the frame image on which the processing unit PU11 performs defect detection and an area for storing the defect information for the defect detected as a result of the defect detection. For convenience, in the following description, the frame image storing area and the defect information storing area allocated in the memory M11 are referred to as the image memory IM11 and the defect information memory DM11, respectively.
The processor element, line counter, memory, image memory, and defect information memory provided in the yth processing unit PUxy within the xth multiprocessing unit MPx are respectively referred to as the processor element PExy, the line counter LCxy, the memory Mxy, the image memory IMxy, and the defect information memory DMxy.
Each processing unit PUxy selects, from the image data corresponding to the channel input to the multiprocessing unit MPx, the frame (inspection frame) to be inspected for defects and stores the selected frame in the image memory IMxy.
For this purpose, the processor unit PUx specifies the range of lines that covers the inspection frame to be inspected by the processing unit PUxy.
As the image capturing unit 12 is scanned by moving the stage 11, the position of the stage 11 is measured by a stage position measuring unit 50. Based on the position information of the stage 11 thus measured, a die switch signal generating unit 51 generates a die switch signal that indicates whether the image capturing unit 12 is currently scanning an inspection region (for example, a chip region) on the wafer 100 or scanning a non-inspection region (for example, an inter-chip region).
The line counter LCxy provided in each processing unit PUxy counts the number of lines of the image data so far received since the die switch signal began to indicate “CURRENTLY SCANNING THE INSPECTION REGION.” The processor element PExy determines whether the number of lines counted (i.e., the line of the image data currently being received) falls within the range of lines specified by the processor unit PUx; if it falls within the specified range, the processor element PExy determines that the image data currently being received corresponds to the inspection frame, and stores the data in the image memory IMxy.
The m frames generated as the image capturing unit 12 scans across the wafer 100 are sequentially input into the processing units PUx1, PUx2, PUx3, . . . , PUxy in this order, after which the subsequently generated frames are sequentially input into the processing units PUx1, etc. in like manner, repeating the same process.
When the inspection frame is stored in the image memory IMxy, the processor element PExy registers the inspection frame with the reference frame against which the inspection frame is to be compared in the subsequent defect detection process.
Here, the number of lines, i, forming each frame is predetermined based on the repeat pitch of the dies or cells on the wafer 100 so that the frames containing patterns that should normally be identical to each other are cyclically input to the same processing unit PUxy.
The frame input to the processing unit PUxy in the immediately preceding cycle is used as the reference frame for the frame input in the current cycle. Alternatively, the frame input in the current cycle is used as the reference frame, and the frame input in the immediately preceding cycle is used as the inspection frame.
The processor element PExy performs the defect detection on the inspection frame. That is, the processor element PExy compares the gray level values of corresponding pixels between the two frames, and if there is a portion where the gray level difference is larger than a threshold value, that portion is detected as containing a defect.
Then, defect information of a prescribed format, indicting the detected position of the defect, the size of the defect, etc., is created for each detected defect, and sent to the processor unit PUx. The processor unit PUx receives the defect information in parallel from the processor element PEx1 to PExm provided in the respective processing units PUx1 to PUxm, and consolidates the defect information into a set of defect information which is then sent to the image processing management unit 21.
The defect information created by the processor element PEx1 to PExm may include defect information created based on a false defect, not a true defect. Accordingly, the processor unit PUx reexamines the defect information received from the respective processor element PEx1 to PExm and determines whether the defect information represents a true defect or a false defect.
FIG. 6 is a time chart showing the conventional operation of the component elements of the multiprocessing unit MPx. The time chart of FIG. 6 shows that when the image capturing unit 12 scans the surface of the wafer 100, the regions on the surface of the wafer 100 to be inspected by the respective processor elements PEx1, PEx2, PEx3, . . . , PExm are scanned by the image capturing unit 12 during the time periods of t1 to t2, t2 to t3, t3 to t4, . . . , t5 to t6, respectively.
During the time period of t1 to t2 when the image capturing unit 12 scans the region on the surface of the wafer 100 to be inspected by the processor element PEx1, the processor element PEx1 acquires the frame corresponding to that region from the image capturing unit 12 and stores the frame in the image memory IM1. Then, after performing “preprocessing” such as the registration between the inspection frame and the reference frame, defect information is generated by performing the defect detection. After that, at time t11, the processor element PEx1 transfers the thus generated defect information to the processor unit PUx together with analysis data necessary for reexamining the defect.
Thereafter, during the time periods of t2 to t3, t3 to t4, . . . , t5 to t6 when the image capturing unit 12 scans the regions on the surface of the wafer 100 to be inspected by the respective processor elements PEx2, PEx3,. . . , PExm, the respective processor elements PEx2, PEx3, . . . , PExm, like the processor element PEx1, acquire the frames corresponding to the respective regions, perform the preprocessing, perform the defect detection, and transfer the defect information and the analysis data to the processor unit PUx.
For the processing unit PUx to reexamine the defect information, not only the defect information indicating the result of the defect detection performed by the processor element PExy, but also the original image from which the defect was detected is needed. Accordingly, the processor element PExy transfers the defect information to the processing unit PUx together with sub-images showing the defect and its surrounding areas segmented from the inspection frame and the reference frame, respectively, as the analysis data. FIG. 7 is a diagram showing by way of example the sub-images segmented as the analysis data from the inspection frame and the reference frame, respectively.
The analysis data that the processor unit PUx uses for reexamination includes sub-image data PId which represents a region of width Wd and length Ld centered around the defect position Pd (x,y) of the defective portion D in the swath image SW and segmented from the inspection frame Fi from which the processor element PExy detected the defect.
The analysis data further includes sub-image data PIr which represents a region corresponding to the position of the sub-image data PId in the inspection frame Fi and segmented from the reference frame Fr against which the inspection frame Fi was compared for the detection of the defect.
When the defect information and the analysis data are received from the processor element PEx1 at time t11, the processor unit PUx reexamines the defect information using the analysis data and determines whether the defect is a true defect or a false defect.
Then, only for the defect verified as being a true defect, “feature amount extraction” is performed to extract feature amounts, such as the size and average gray level of the defect, the average gray level difference between the inspection image and the reference image, etc., and the defect information is classified according to the extracted feature amounts.
Thereafter, when the defect information and the analysis data are received from the processor elements PEx2 and PEx3 at times 12 and t13, respectively, the processor unit PUx reexamines the defect information, extracts the feature amounts of the defects, and classifies the defects, in the same manner as when the defect information and the analysis data are received from the processor element PEx1.
Then, after time t6, the regions to be inspected for defects by the respective processor elements PEx1, PEx2, PEx3, . . . , PExm are scanned by the image capturing unit 12 in the same manner as described above, repeating the same process.
As described above, in the prior art image defect inspection apparatus, the plurality of processor elements PExy perform the defect detection in parallel, and transfer the defect information of the detected defects to the processor unit PUx which consolidates the defect information into a set of defect information; in this case, reexamination of the defect information is performed on the processor unit PUx side. As a result, the amount of data to be transferred from the processor elements PExy to the processor unit PUx becomes excessively large for the following reasons.
First, since the defects detected by the plurality of processor elements PExy include false defects, the defect information that the processor elements PExy transfer to the processor unit PUx includes false defect information which otherwise need not be transferred.
Second, since the reexamination of the defect is performed on the processor unit PUx side, analysis image data has to be transferred from each processor element PExy, increasing the amount of data to be transferred for each defect.
In this way, in the prior art image defect inspection apparatus, since the amount of data transferred to the processor unit PUx is large, the processing capacity of the processor unit PUx becomes a bottleneck, limiting the number of defects that can be detected by each processor element PExy and thus preventing the defect detection sensitivity from being increased. As a result, there arises the possibility that a true defect may not be detected as a defect candidate in the defect detection performed by each processor element PExy.